A Low Power Pipelined FFT/IFFT Processor for OFDM Applications

To produce multiple subcarriers orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT).This paper, present the efficient implementation of a pipeline FFT/IFFT processor for OFDM applications. This design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROM’s) used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works. KEYWORD: single-path delay feedback, bit-parallel multipliers, low power. I.INTRODUCTION Due to the popularity of the communication systems, the Fourier transform is still one of research and development topics in the radio transmission and mobile communication. However, for the operation of discrete Fourier transform in real-time signal processing system, it is important to get the operation results in time. Therefore, fast Fourier transform (FFT) is the suitable choice for this purpose since the computational complexity is reduced from O(N)to O(N log N) . The high-speed performance and hardware reduction can be attained. The main trends of FFT hardware development are towards high throughput and low power consumption. The pipelined structure is the most common choice for high-throughput FFT processor. Many methods have been proposed to implement the pipelined FFT hardware architectures. They can be categorized into three kinds, namely, the multiple-path delay commutator (MDC), single-path delay feedback (SDF), and single-path delay commutator (SDC) architectures. In comparison with the three pipeline architectures, the SDF architecture is the most suitable for FFT implementation. Its advantages are (i).the SDF architecture is very simple to implement the different length FFT, (ii).the required registers in SDF architecture is less than MDC and SDC architectures,(iii).The control unit of SDF architecture is easier than the others. A. DISCRETE FOURIER TRANSFORM Discrete Fourier transform (DFT) is a very important technique in modern digital signal processing (DSP) and telecommunications, especially for applications in orthogonal frequency demodulation multiplexing (OFDM) systems, such as IEEE 802.11a/g , Worldwide Interoperability for Microwave Access (WiMAX) , Long Term Evolution(LTE), and Digital Video Broadcasting—Terrestrial(DVB-T) . However, DFT is computational intensive and has a time complexity of O(N2). The fast Fourier Transform (FFT) was proposed by Cooley and Tukey to efficiently reduce the time complexity to O (N log 2N), where N denotes the FFT size. For hardware implementation, various FFT processors have been proposed. These implementations can be mainly classified into memory-based and pipeline architecture styles. Memory-based architecture is widely adopted to design an FFT processor, also known as the single processing element (PE) approach. This design style is usually composed of a main PE and several memory units, thus the hardware cost and the power consumption are both lower than the other ISSN (Print) : 2320 – 3765 ISSN (Online): 2278 – 8875 International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (An ISO 3297: 2007 Certified Organization) Vol. 2, Issue 10, October 2013 Copyright to IJAREEIE www.ijareeie.com 4713 architecture style. However, this kind of architecture style has long latency, low throughput, and cannot be parallelized. On the other hand, the pipeline architecture style can get rid off the disadvantages of the foregoing style, at the cost of an acceptable hardware overhead. The single-path delay feedback (SDF) pipeline FFT is good in its requiring less memory space (about N-1 delay elements) and its multiplication computation utilization being less than 50%, as well as its control unit being easy to design. Such implementations are advantageous to low-power design, especially for applications in portable DSP devices. Based on these reasons, the SDF pipeline FFT is adopted in this work. However, the FFT computation often needs to multiply input signals with different twiddle factors for an outcome, which results in higher hardware cost because a large size of ROM is needed to store the wanted twiddle factors. Therefore, to throw off these ROM’s for area-efficient consideration. B.COMPLEX MULTIPLIERS The complex multipliers used in the processor are realized with shift-and-add operations. Hence, the processor uses only a two-input digital multiplier and does not need any ROM for internal storage of coefficients. However, low speed and higher hardware cost caused by the proposed complex multiplier are the pay-off. In order to further improve the power consumption and chip area of previous works, this paper proposes an efficient radix-2 pipeline architecture with low power consumption for the FFT/IFFT processor. The proposed architecture includes a reconfigurable complex constant multiplier and bit-parallel complex multipliers instead of using ROM’s to store twiddle factors, which is suited for the power-of-2 radix style of FFT/IFFT processors. II.METHODOLOGY A. ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING OFDM is the abbreviation for Orthogonal Frequency Division Multiplexing, and describes a digital modulation scheme that distributes a single data stream over a large number of carriers for parallel transmission. These carriers are called the subcarriers of the signal. In the frequency domain, they are equally spaced around a central RF carrier, so the frequency fn,rf of the nth subcarrier out of N can be expressed as fn,rf=fc+n.fd, with (1) nє[, ] if N is odd and (2) nє[, -1] if N is even. (3) fd is the frequency spacing between the subcarriers and fc is the center frequency of the OFDM signal. In the baseband, we obtain fn=n.fd, with (4) nє[, ] for odd and (5) nє[, -1] for even (6) where fn is the baseband frequency of the nth subcarrier. ISSN (Print) : 2320 – 3765 ISSN (Online): 2278 – 8875 International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (An ISO 3297: 2007 Certified Organization) Vol. 2, Issue 10, October 2013 Copyright to IJAREEIE www.ijareeie.com 4714 The subcarriers exp(2*Pi*n*fd*t) build an orthogonal set of functions, hence the name of the modulation. Each of these subcarriers is modulated separately. The modulation symbols result from encoding the binary data using traditional PSK or QAM mappings. Let us assume we want to transmit 128 bits simultaneously on N = 64 QPSK modulated subcarriers (n = -32, -31..., +31). Then for example the subcarrier with index -32 may carry the first pair of bits, the subcarrier with index -31 would carry thesecond pair, and so on. The last two bits would then be assigned to the subcarrier with index +31. So, within one OFDM symbol, each subcarrier has its own phase pn and amplitude an. The whole baseband signal looks like this: (7) Where nmin and nmax set the range for n. We can interpret this as the Discrete Fourier Transform (DFT) of the OFDM symbol to generate. Consequently, instead of really modulatingall 64 subcarriers, the discrete time domain signal is calculated by applying to s an inverse DFT of length N. The result is a series of samples that represent one period of a signal that has the same spectrum as the desired OFDM symbol. The sampling frequency is fs = N*fd. One period of the calculated series yields all amplitude and phase information contained in s. The minimum OFDM Symbol duration is thus